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TRF7970A
www.ti.com
SLOS743K – AUGUST 2011 – REVISED APRIL 2014
Default: reset to 00 at POR and EN = L. B0 to B4 are automatically reset after MCU read operation. B6
and B7 continuously display the RF level comparator outputs.
Based on the first command from INITIATOR following actions are taken:
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If the first command is SENS_REQ or ALL_REQ, the TARGET must enter the SDD protocol for 106
kbps passive communication. If bit B5 in NFC Target Detection Level register is not set, the MCU
handles the SDD and the command received is send to FIFO. If the RF field is turned off (B7 in the
NFC Target Protocol register goes low) at any time, the system sends an IRQ to the MCU with bit B2
(RF field change) in the IRQ register set high. This informs the MCU that the procedure was aborted
and the system must be reset. The clock extractor is automatically activated in this mode.
If the command is SENS_REQ or ALL_REQ and the Tag emulation bit in ISO Control register is set,
the system emulates an ISO14443A tag. The procedure does not differ from the one previously
described for a passive target at 106 kbps. The clock extractor is automatically activated in this mode.
If the first command is a POLLING request, the system becomes a TARGET in passive communication
using 212 kbps or 424 kbps. The SDD is relatively simple and is handled by the MCU directly. The
POLLING response is sent in one of the slots automatically calculated by the MCU (first slot starts
2.416 ms after the end of the command and slots follow in 1.208 ms).
If the first command is ATR_REQ, the system operates as an active TARGET using the same
communication speed and bit coding as used by the INITIATOR. Again, all of the replies are handled
by MCU. The chip is only required to time the response collision avoidance, which is done on direct
command from MCU. When the RF field is switched on and the minimum wait time is elapsed, the chip
sends an IRQ with B1 (RF collision avoidance finished) set high. This signals the MCU that it can send
the reply.
If the first command is coded as ISO14443B and the Tag emulation bit is set in the ISO Control
register, the system enters ISO14443B emulator mode. The anticollision must be handled by the MCU,
and the chip provides all physical level coding, decoding, and framing for this protocol.
Table 6-18 shows the function of the IRQ and Status register in NFC and Tag emulation. This register is
preset to 0 at POR = H or EN = L and at each write to ISO Control. It is also automatically reset at the end
of read phase. The reset also removes the IRQ flag.
Table 6-18. IRQ and Status Register (0x0C) for NFC and Card Emulation Operation
(1)
Bit
Name
Function
Description
Signals that TX is in progress. The flag is set at the start of
B7
Irq_tx
IRQ set due to end of TX
TX but the interrupt request (IRQ = 1) is sent when TX is
finished.
Signals that RX SOF was received and RX is in progress.
B6
Irg_srx
IRQ set due to RX start
The flag is set at the start of RX but the interrupt request
(IRQ = 1) is sent when RX is finished.
B5
B4
B3
B2
Irq_fifo
Irq_err1
Irq_err2
Irq_err3
Signals the FIFO level
CRC error
Parity error
Byte framing or EOF error
Signals FIFO high or low as set in the Adjustable FIFO IRQ
Levels (0x14) register
Indicates receive CRC error only if B7 (no RX CRC) of ISO
Control register is set to 0.
Indicates parity error for ISO14443A
Indicates framing error
Collision error for ISO14443A and ISO15693 single
subcarrier. Bit is set if more then 6 or 7 (as defined in
B1
Irq_col
Collision error
register 0x01) are detected inside one bit period of
ISO14443A 106 kbps. Collision error bit can also be
triggered by external noise.
No response within the "No-response time" defined in RX
B0
Irq_noresp
No-response time interrupt
No-response Wait Time register (0x07). Signals the MCU
that next slot command can be sent. Only for ISO15693.
(1)
Displays the cause of IRQ and TX/RX status
Copyright ? 2011–2014, Texas Instruments Incorporated
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